System on a chip (SoC) integrated circuits may have its memory controller centrally located on the SOC die whereas the endpoints (I/O circuits) that interface with an external memory may be located on the die periphery. Given this separation between the memory controller and the endpoints, synchronization of data across the endpoints becomes increasingly more difficult. For example, during a write operation to the external memory such as to a dynamic random access memory (DRAM, the memory controller launches data words and a clock to the endpoints. The data words must arrive relatively synchronously at each endpoint to conform to the strict timing requirements of the external memory. In particular, each of the endpoints may be required to send data words to the DRAM on the same clock cycle or clock edge. This timing requirement represents numerous challenges and problems that may be better appreciated with reference to an example conventional SOC 100 shown in FIG. 1.
In SOC 100, a memory controller 105 transmits data to a number of endpoints including an endpoint 115 and an endpoint 120. Since endpoints 115 and 120 then launch the data to an external memory, they are located at the periphery of SOC 100 (endpoints 115 and 120 may represent just a subset of the total endpoints for illustration clarity). A clock source such as a phase-locked loop (PLL) 110 is located proximate to the endpoints 115 and 120. Given this proximity, PLL 110 transmits a clock signal that arrives relatively synchronously at each endpoint 115 and 120. In contrast to this proximity of PLL 110 to endpoints 115 and 120, memory controller 105 is centrally located on the die and is thus relatively distant from PLL 110, which also sends the clock signal across the SOC 100 to memory controller 105. Memory controller 105 then re-transmits the clock on a separate clock path to each endpoint 115 and 120. In addition, memory source 105 launches data (e.g., data words) on separate data paths to each endpoint 115 and 120. The endpoints register the launched data according to an edge of the clock received from memory controller 105 and retransmit the data to an external memory (not illustrated) responsive to an edge of the clock received from PLL 110.
Since memory controller 105 is typically located in a central region of the SOC 100, each endpoint's clock path and data path must traverse a relatively large distance of the SOC die to extend from memory controller 105 to the respective endpoints. By traversing across such relatively long paths, the clock and data carried on these path will be subject to a number of respective variations (e.g., device variations, temperature changes, voltage noise, jitter, path length, etc.) that may be unique to a given data path or clock path. As such, respective data words and the corresponding clock may arrive at each of the endpoints 115 and 120 asynchronously, thereby creating data alignment issues with the strict timing requirements of the external memory. It is thus conventional to carefully align and electrically match the data and clock paths for endpoint 115 to endpoint 120 to so minimize this asynchronicity. But this alignment is expensive and cumbersome to implement.
Accordingly, there is a need in the art for improving the synchronization of endpoints.